Results-oriented Physical Design Engineer specializing in STA, SI signoff, and PDN analysis for advanced semiconductor designs down to 3nm. Proven ability to close timing and power integrity on complex SoCs, driving PPA improvements. Adept at cross-functional collaboration and leveraging automation for enhanced efficiency. Currently innovating with AI/ML agents for design and signoff.
Anubhav Kumar
Physical Design Sign-off Hardware Engineer
Profile
Experiences
Qualcomm
[Full-time]
Jul 2020 - Present
Senior Hardware Engineer
Bengaluru, Karnataka, India
- Led STA closure for high-performance Cores (GPU/SOC), achieving ~10% frequency increase and 22% leakage/area recovery via clock/logic optimization.
- Drove sub-10nm SoCs PDN Signoff (IR/EM/ESD), improving VCD IR drop margin by 60mV and reducing TAT by 28% via automation/placement strategies.
- Expertise in Implementing Timing, Power, Area/Leakage ECOs, resolving TDRC violations and optimizing PG grid, IR drop, EM, and inrush.
- Developed/deployed automation scripts (GDHS, Inrush, PDN, STA, CLP), significantly reducing manual effort and improved runtime.
- Accelerated ECO turnaround by 60% through selective Timing what-if analysis for PDN drops.
- Developed RAG LLM chat web interface for team knowledge access and AI agents for automating PD/signoff.
- Collaborated with cross-functional teams (Design, Synthesis, Verification, Constraints, RDL) for robust design and signoff.
- Integrated IP blocks and managed static/analog routing for STA/PDN signoff.
- Proficient in Synopsys (PrimeTime, PT-SI, Tweaker, DC), Cadence (Tempus, Tempus-SI, Voltus, Virtuoso, CLP), and Ansys (Redhawk-SC, Pathfinder-SC) EDA tools.
- Skilled in Tcl, Shell, Python, and Perl scripting.
Bharat Electronics Limited
[Full-time]
Mar 2018 - Jul 2018
Dy Engineer
Bengaluru, Karnataka, India
Design and development of logic circuit boards for Electronic Voting Machines (EVM) and VVPATs.
Lava International Limited
[Full-time]
Jun 2016 - Sep 2017
QA/QC Engineer
Bengaluru, Karnataka, India
Hardware QA and Reliability Assurance.
Skills
Programming Languages
Python
Tcl-Tk
Perl
Verilog RTL
HTML-JS-CSS
EDA tools
STA (PrimeTime, Tempus)
PDN (Redhawk-SC, Voltus, HSPICE)
PD (Innovus, Fusion Compiler)
others (Conformal, MATLAB, Vivado)
AI/ML
Data Analysis
Tensorflow
LLMs
RAG
OS
Unix
NixOS
Windows - Mac
Education
2018 - 2020
M.Tech, Microelectronics and VLSI
Master
Worked on the below MHRD and industry sponsered Projects .
- An Energy-Efficient In-Memory Processor Using CMOS SRAM.
- Aging Aware Delay-Model for Robust Timing signoff.
LPU Jalandhar, India
2012 - 2016
Electronics and Communication Engineering
Bachelor
comprehensive coursework from Electronic Design to software integration.
- Developed audio tools like cleaning, amplifying and real time translation with app (MATLAB, Audrino & Android).
Certificates
DeepLearning.AI
2020
Deep Learning Specialization Covering From Neural Networks to Transformers Hyperparameters Tuning and optimization.
Johns Hopkins University
2020
University of Illinois
2024
Learning the core concepts behind building the CAD software tools for EDA automation and methodology.
Publications
- Developed a method for device-level variability-aware STA using Python and Bash scripting.
- Created an Effective Current Source Model (ECSM) .libs file with custom tool flow.
- Integrated variation-aware timing models into industry-standard STA tools.
- Conducted simulations using Mentor Graphics ELDO SPICE, Synopsys DC Compiler, and PrimeTime.
- Achieved 98.13% reduction in recharacterization efforts compared to conventional SPICE simulation.
- Utilized STMicroelectronics (STM) 65 nm CMOS process for simulation work.
- Qualcomm (GPU PPA improvements within constrained Timelines) Global GSOC internal Publication.
Eliza CX PPA Challenges & Solutions: GPU Case Study
Qualcomm GSOC, 2025
Awards
IIT Roorkee
2020
For contribution towards the IEEE published research work for Variability-Aware STA methodology.
QualStar
Qualcomm
20222024
- 2022: For contribution towards multiple SOC PDN signoff.
- 2024: For contribution towards developing STA automation for the GDHS/APM chaining and inrush checks.
Organizations
- Placement Coordinator at Training and Placement cell, IIT Roorkee (2019-2020): Connecting and coordinating Semiconductor companies for the Recruitment Processes.
- High Altitude Trek Leader at Himalayan Explorer Club, IIT Roorkee (2019-2020): Led multiple sports activities and High-Altitude Mountain Treks reaching peak of ~5000m.
Languages
English
[Professional]
Hindi
[Native]
Interests
Cooking