ASIC

Power Straps

3 min read

Power Straps in VLSI Power Delivery Network

Simple Explanation (Gist)

Power straps are horizontal and vertical metal lines that form a grid-like structure within the Power Grid of a VLSI chip, distributing power (Vdd) and ground (Vss) from the Power Rings to the individual standard cells and other logic blocks.

Detailed Breakdown

  • Motivation: Power straps are essential for providing a robust and low-impedance path for power and ground to all parts of the chip. They work in conjunction with Power Rings and Power Rails to ensure stable voltage delivery, minimize IR Drop, and reduce noise.

  • Concept: Power straps are typically implemented on multiple metal layers, forming an orthogonal mesh. For example, horizontal straps might be on Metal 6 and vertical straps on Metal 7. This grid structure provides multiple redundant paths for current, which helps in distributing current more uniformly and mitigating localized voltage drops.

  • Key Characteristics:

    • Grid Structure: Form a mesh-like network across the chip’s core area.
    • Multi-Layer: Utilized on various metal layers, with higher layers often used for wider, more global straps due to their lower resistance.
    • Redundancy: Provide multiple current paths, improving reliability and robustness against localized defects or electromigration.
    • Connection to Rings: Connected to the Power Rings (which typically encircle the core and macros) through numerous vias.
    • Connection to Rails: Connect to the Power Rails (which run within standard cell rows) to deliver power directly to the gates.
    graph TD
    A[Power Rings] --> B[Power Straps (Horizontal)];
    A --> C[Power Straps (Vertical)];
    B -- Vias --> C;
    B --> D[Power Rails];
    C --> D;
    D --> E[Standard Cells / Logic];

  • Role in the Power Delivery Network (PDN):

    • Power straps are an intermediate level of power distribution, bridging the gap between the global Power Rings and the local Power Rails.
    • They are crucial for ensuring that current is distributed evenly across the chip, preventing hot spots and localized IR drop issues.

  • Design Considerations:

    • Width and Spacing: The width and spacing of power straps are critical design parameters, determined by the total current demand, acceptable IR drop, and electromigration limits. Wider straps reduce resistance and improve current carrying capability.
    • Via Density: Sufficient and robust via connections between different layers of straps and to the power rails are essential to minimize resistance and ensure efficient current flow.
    • Metal Layer Selection: Higher metal layers are often preferred for power straps due to their lower sheet resistance and larger pitch, which allows for wider lines.
    • Electromigration: Power straps must be designed to withstand the current densities without suffering from Electromigration over the chip’s lifetime.
    • Decoupling Capacitors: Decoupling capacitors are often placed within the power mesh to provide local charge reservoirs and mitigate dynamic IR drop.

Further Reading

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