ASIC

_ASIC Design Flow

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ASIC Chip Design Flow: A Comprehensive Guide

Table of Contents

ASIC Design Flow

A visual representation of the entire flow, including key inputs, outputs, and iteration loops.

graph TD
    A[Chip Specification] --> B[RTL Design-Verilog/HDL];
    B --> C{Functional Verification};
    C -- Fixes --> B;
    C --> D[Synthesis-Gate Level Netlist];
    D --> E[Design for Test-scandef];
    E --> F[Physical Design-def];
    
    F -- Optimization --> D;

    F --> G[Signoff-STA/PDN/PV/CLP etc.];
    G -- Iterations --> F;
    G --> H[Tape Out-GDSII];
    
    H --> I[Post-Silicon Validation];
    I -- Silicon Bugs --> A;

    style F fill:#f9f,stroke:#333,stroke-width:2px
    style G fill:#ccf,stroke:#333,stroke-width:2px

1. Chip Specification

Where the idea and requirements for the ASIC are defined.

2. RTL Design

Translating the microarchitecture into a hardware description language.

3. Functional Verification

Ensuring the RTL design behaves as intended before synthesis.

4. Synthesis

Converting RTL code into a technology-specific gate-level netlist.

5. Design for Test (DFT)

Adding logic to the design to facilitate manufacturing testability.

6. Physical Design

Creating the physical layout of the chip from the netlist.

6.1. Pre-Placement & Sanity Checks

6.2. Floorplanning & Power Planning

6.3. Placement

6.4. Clock Tree Synthesis (CTS)

6.5. Routing

7. Sign Off

Final verification checks before manufacturing.

7.1. Static Timing Analysis (STA)

Analyzing timing paths to ensure the design meets timing and frequency requirements across all PVT conditions.

7.2. Power Signoff

Ensuring power integrity, reliability, and compliance in low-power, multi-voltage designs.

7.3. Physical Verification

7.4. ECO - Engineering Change Order

8. Tape Out & Manufacturing

Sending the final design to the foundry.

9. Post-Silicon Validation

Testing the manufactured chip in a lab environment.

Books

  • Digital Design & Computer Architecture
    • Computer Architecture: A Quantitative Approach by John L. Hennessy & David A. Patterson
    • Digital Design and Computer Architecture by David Money Harris & Sarah L. Harris
    • Computer Organization and Design by David A. Patterson & John L. Hennessy
  • HDL (Verilog/VHDL/SystemVerilog)
    • Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog by M. Morris Mano & Michael D. Ciletti
    • RTL Modeling with SystemVerilog for Simulation and Synthesis by Stuart Sutherland
    • The Designer’s Guide to VHDL by Peter J. Ashenden
  • Functional Verification & UVM
    • SystemVerilog for Verification: A Guide to Learning the Testbench Language Features by Chris Spear
    • The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology by Ray Salemi
    • Cracking Digital VLSI Verification Interview by Ramdas Mozhikunnath
  • Synthesis & Static Timing Analysis (STA)
    • Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime® by Himanshu Bhatnagar
    • Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) by Sridhar Gangadharan & Sanjay Churiwala
    • Static Timing Analysis for Nanometer Designs: A Practical Approach by J. Bhasker & Rakesh Chadha
    • Logic Synthesis and Verification by Soha Hassoun & Tsutomu Sasao
  • Physical Design
    • Physical Design Essentials: An ASIC Design Implementation Perspective by Khosrow Golshan
    • CMOS VLSI Design: A Circuits and Systems Perspective by Neil Weste & David Harris
  • Power Integrity
    • Power Integrity Analysis and Management for Integrated Circuits by Raj Nair & Donald Bennett
    • The Printed Circuit Designer’s Guide to Power Integrity by Example by Fadi Deek
  • Design for Test (DFT) & Post-Silicon Validation
    • Post-Silicon Validation and Debug by Prabhat Mishra & Farimah Farahmandi
    • The Small Book About Design-for-Test by Juergen Alt
    • VLSI Test Principles and Architectures by Laung-Terng Wang, Cheng-Wen Wu, & Xiaoqing Wen

Websites & Blogs

11. Key File Formats

Extension(s)Full NameDescription
.v, .vh, .sv, .svhVerilog / SystemVerilogRTL or Gate-Level Netlist
.vhd, .vhdlVHDLRTL or Gate-Level Netlist
.sdcSynopsys Design ConstraintsTiming, power, and area constraints
.lib, .dbLiberty Timing LibraryStandard cell timing and power models
.lefLibrary Exchange FormatPhysical abstract view of cells/macros
.defDesign Exchange FormatPhysical layout data (placement, routing)
.spefStandard Parasitic Exchange FormatExtracted parasitic R and C values
.gds, .gdsii, .oasGDSII or OASISFinal layout database for manufacturing
.upf, .cpfUnified/Common Power FormatLow-power design intent
.tfTechnology FileFoundry process layer information
.vcd, .saifActivity Vectors, Value Change Dump , SAIFSwitching activity for power analysis

12. Key EDA Tools

Design StageSynopsysCadenceSiemens EDA
RTL DesignVCSXceliumQuesta
SynthesisFusion Compiler, Design CompilerGenusTessent Synthesis
Formal VerificationFormalityConformal LECTessent Formal
Static Timing Analysis (STA)PrimeTime (PT)TempusTessent Shell with STA
CTSPrimeTime (PT)TempusTessent Shell with STA
CTSPrimeTime (PT)TempusTessent Shell with STA
CTSPrimeTime (PT)TempusTessent Shell with STA
Design for Test (DFT)TestMAXModusTessent
Physical DesignIC Compiler II (ICC2)InnovusAprisa
Parasitic ExtractionStarRCQuantusCalibre xACT
Physical Verification (DRC/LVS)IC Validator (ICV), HerculesPegasusCalibre
Power SignoffPrimePower, RedHawk (Ansys)VoltusCalibre PERC, mPower

13. Frontend Interview Questions

Basic Questions for each topic for checking the knowledge level. Do you know them all?

14. Backend Interview Questions

Graph View

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