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Tag: VLSI
152 items with this tag.
Jul 24, 2025
Conformal Low Power (CLP) Checks
VLSI
Low-Power-Design
Power-Management
Verification
EDA
Jul 24, 2025
CTS Tools
VLSI
Physical-Design
CTS
EDA-Tools
Clocking
Jul 24, 2025
DCD in VLSI
VLSI
Timing
Signal-Integrity
Verification
Design-Flow
Jul 24, 2025
DDR (Double Data Rate) SDRAM
VLSI
Memory
Interface
Physical-Design
SoC
Jul 24, 2025
Design Exchange Format (DEF)
VLSI
Physical-Design
File-Format
EDA
Jul 24, 2025
DFT Principles in VLSI
VLSI
DFT
Testability
ASIC
Verification
Jul 24, 2025
Design for Test (DFT)
VLSI
DFT
Testability
ASIC
Verification
Jul 24, 2025
Design Rule Check (DRC)
VLSI
Physical-Verification
DRC
Manufacturing
ASIC
Jul 24, 2025
DRV Fixing in VLSI
VLSI
Physical-Design
DRC
Timing-Closure
ASIC
Jul 24, 2025
Data Path Design
VLSI
Physical-Design
Datapath
ASIC
Jul 24, 2025
Debugging in VLSI
VLSI
Verification
Debug
ASIC
Post-Silicon
Jul 24, 2025
Decap Planning in VLSI
VLSI
Physical-Design
Power-Integrity
Decaps
ASIC
Jul 24, 2025
Decaps in VLSI
VLSI
Power-Integrity
Decoupling-Capacitors
ASIC
Noise
Jul 24, 2025
Delay Models in VLSI
VLSI
Timing-Analysis
Delay
ASIC
Jul 24, 2025
Delay in VLSI
VLSI
Timing
Performance
ASIC
Jul 24, 2025
Density Checks in VLSI
VLSI
Physical-Verification
Manufacturing
DRC
Jul 24, 2025
Die Size Estimation in VLSI
VLSI
Physical-Design
Semiconductor-Manufacturing
Die-Size
Estimation
Jul 24, 2025
Digital Logic in VLSI
VLSI
Digital-Logic
CMOS
Integrated-Circuits
Semiconductor
Jul 24, 2025
Directed Testing
VLSI
Verification
Test
ASIC
Jul 24, 2025
Double Patterning Check (DPC) in VLSI
VLSI
Lithography
Manufacturing
Physical-Verification
Advanced-Nodes
Jul 24, 2025
Dynamic Power in VLSI
VLSI
Power-Consumption
Low-Power-Design
ASIC
Jul 24, 2025
Engineering Change Order (ECO) in VLSI
VLSI
ASIC
Design-Flow
Manufacturing
Bug-Fix
Jul 24, 2025
Electrical Rule Check (ERC)
VLSI
Physical-Verification
Electrical-Check
ASIC
Jul 24, 2025
ESD Checks in VLSI
VLSI
ESD
Reliability
Physical-Verification
ASIC
Jul 24, 2025
Electromigration in VLSI
VLSI
Reliability
Interconnect
Physical-Design
Power-Integrity
Jul 24, 2025
Emulation & Prototyping & FPGA
VLSI
Verification
FPGA
Emulation
Prototyping
Jul 24, 2025
False Paths in STA
VLSI
Timing-Analysis
STA
ASIC
Timing-Exceptions
Jul 24, 2025
Fault Models in VLSI
VLSI
Test
DFT
Verification
ASIC
Jul 24, 2025
Finite State Machines (FSM)
VLSI
RTL-Design
Digital-Logic
Jul 24, 2025
Floating Nets and Pins in VLSI
VLSI
Design-Issues
Signal-Integrity
Power-Integrity
Verification
Jul 24, 2025
Floorplanning and Power Planning in VLSI
VLSI
Physical-Design
Floorplanning
Power-Planning
ASIC
Jul 24, 2025
Flylines
VLSI
Physical-Design
Floorplanning
Jul 24, 2025
Formal Verification
VLSI
Functional-Verification
Verification-Methodologies
Jul 24, 2025
Foundry
VLSI
Tape-Out
Manufacturing
Jul 24, 2025
Functional ECO
VLSI
ECO
Functional-Verification
Jul 24, 2025
Functional Specification
VLSI
ASIC-Design
Chip-Specification
Jul 24, 2025
Functional Verification
VLSI
ASIC-Design
Verification
Jul 24, 2025
GDSII or OASIS
VLSI
Tape-Out
Manufacturing
Jul 24, 2025
GPU
VLSI
ASIC-Design
Chip-Specification
Jul 24, 2025
Gate-Level Netlist
VLSI
Synthesis
Netlist
Jul 24, 2025
Global Routing
VLSI
Physical-Design
Routing
Jul 24, 2025
H-Tree
VLSI
Clock-Tree-Synthesis
Physical-Design
Jul 24, 2025
HDL
VLSI
RTL-Design
HDL
Jul 24, 2025
Hierarchical Synthesis
VLSI
Synthesis
Design-Flow
Jul 24, 2025
High-Fanout Net Synthesis (HFNS)
VLSI
Physical-Design
Placement
Jul 24, 2025
Hold Time
VLSI
STA
Timing-Analysis
Jul 24, 2025
I-O Specification
VLSI
Chip-Specification
Design-Flow
Jul 24, 2025
IP Integration
VLSI
RTL-Design
IP
Jul 24, 2025
IR Drop Aware Timing Signoff
VLSI
STA
Power-Integrity
Signoff
Jul 24, 2025
IR Drop
VLSI
Power-Integrity
Power-Signoff
Jul 24, 2025
In-rush Current
VLSI
Power-Management
Power-Integrity
Jul 24, 2025
Incremental Synthesis
VLSI
Synthesis
Design-Flow
Jul 24, 2025
Intel
VLSI
Foundry
Semiconductor-Manufacturing
Jul 24, 2025
Isolation Cells
VLSI
Low-Power-Design
Synthesis
Jul 24, 2025
JTAG
VLSI
DFT
Testing
Jul 24, 2025
Key EDA Tools
VLSI
EDA-Tools
Design-Flow
Jul 24, 2025
Key File Formats
VLSI
File-Formats
Design-Flow
Jul 24, 2025
Latch Inference
VLSI
RTL-Design
Synthesis
Jul 24, 2025
MPW
VLSI
STA
Timing-Violations
Jul 24, 2025
MSCTS
VLSI
Clock-Tree-Synthesis
Physical-Design
Jul 24, 2025
Metal Fill
VLSI
Physical-Design
Manufacturing
Jul 24, 2025
Microarchitecture
VLSI
Chip-Specification
Architecture
Jul 24, 2025
Min Period
VLSI
STA
Timing-Violations
Jul 24, 2025
Modem
VLSI
Chip-Specification
Communication
Jul 24, 2025
Multi-Vt Cells
VLSI
Low-Power-Design
Standard-Cells
Jul 24, 2025
Multi-driven Nets
VLSI
Design-Issues
Sanity-Checks
Jul 24, 2025
Multi-voltage Design
VLSI
Low-Power-Design
Power-Management
Jul 24, 2025
Multicycle Paths
VLSI
STA
Timing-Exceptions
Jul 24, 2025
NDR
VLSI
Physical-Design
Routing
Jul 24, 2025
NLDM
VLSI
STA
Delay-Models
Jul 24, 2025
Netlist Input
VLSI
Physical-Design
Design-Flow
Jul 24, 2025
Netlist
VLSI
STA
Design-Flow
Jul 24, 2025
Noise
VLSI
Signal-Integrity
Physical-Design
Jul 24, 2025
OCV
VLSI
STA
Variability
Jul 24, 2025
Open and Short Faults
VLSI
DFT
Fault-Models
Jul 24, 2025
Operand Isolation
VLSI
Low-Power-Design
Power-Management
Jul 24, 2025
Optimization Techniques
VLSI
Synthesis
Optimization
Jul 24, 2025
PCIe
VLSI
Chip-Specification
Interconnect
Jul 24, 2025
PPA
VLSI
Chip-Specification
Optimization
Jul 24, 2025
PVT Corners
VLSI
STA
Design-Corners
Jul 24, 2025
PV_Tools
VLSI
Physical-Verification
EDA-Tools
Jul 24, 2025
Parameterization
VLSI
RTL-Design
Verilog
SystemVerilog
Jul 24, 2025
Physical Synthesis
VLSI
Synthesis
Physical-Design
Jul 24, 2025
Physical Verification
VLSI
Physical-Design
Verification
Jul 24, 2025
Pin Assignment
VLSI
Physical-Design
Floorplanning
Jul 24, 2025
Pipeline Design
VLSI
Chip-Specification
Architecture
Jul 24, 2025
Placement
VLSI
Physical-Design
P-and-R
Jul 24, 2025
Power Gating
VLSI
Low-Power-Design
Power-Management
Jul 24, 2025
Power Grid
VLSI
Power-Delivery-Network
Power-Integrity
Jul 24, 2025
Power Mesh
VLSI
Power-Delivery-Network
Power-Integrity
Jul 24, 2025
Power Rails
VLSI
Power-Delivery-Network
Power-Integrity
Jul 24, 2025
Power Rings
VLSI
Power-Delivery-Network
Power-Integrity
Jul 24, 2025
Power Signoff
VLSI
Power-Integrity
Signoff
Jul 24, 2025
Power Straps
VLSI
Power-Delivery-Network
Power-Integrity
Jul 24, 2025
Power Types
VLSI
Power-Consumption
Low-Power-Design
Jul 24, 2025
Pre-Placement & Sanity Checks
VLSI
Physical-Design
Verification
Jul 24, 2025
PrimeTime
VLSI
STA
EDA-Tools
Jul 24, 2025
Recommended Resources
VLSI
Resources
Books
Websites
Jul 24, 2025
Recovery
VLSI
STA
Timing-Violations
Jul 24, 2025
Register Retiming
VLSI
Synthesis
Optimization
Jul 24, 2025
Removal
VLSI
STA
Timing-Violations
Jul 24, 2025
Reset Strategy
VLSI
RTL-Design
Reset
Jul 24, 2025
Reset Synchronizer
VLSI
RTL-Design
Reset
CDC
Jul 24, 2025
Chip
ASIC
VLSI
Integrated-Circuit
Jul 24, 2025
report_analysis_coverage
VLSI
STA
PrimeTime
Commands
Jul 24, 2025
report_annotated_parasitics
VLSI
STA
PrimeTime
Commands
Jul 24, 2025
report_clock_timing
VLSI
STA
PrimeTime
Commands
Jul 24, 2025
report_constraint
VLSI
STA
PrimeTime
Commands
Jul 24, 2025
report_delay_calculation
VLSI
STA
PrimeTime
Commands
Jul 24, 2025
report_exceptions
VLSI
STA
PrimeTime
Commands
Jul 24, 2025
report_noise
VLSI
STA
PrimeTime
Timing-Reports
Signal-Integrity
Jul 24, 2025
report_qor
VLSI
STA
PrimeTime
Timing-Reports
Jul 24, 2025
report_timing
VLSI
STA
PrimeTime
Timing-Reports
Jul 23, 2025
Automatic Test Equipment (ATE)
VLSI
Testing
ASIC
ATE
Post-Silicon-Validation
Jul 23, 2025
Automatic Test Pattern Generation (ATPG)
VLSI
Testing
ASIC
DFT
ATPG
Jul 23, 2025
Activity Vectors
VLSI
Power-Analysis
ASIC
SAIF
VCD
Jul 23, 2025
Advanced Verification in VLSI
VLSI
Verification
ASIC
UVM
Formal
PSS
AI
Jul 23, 2025
Antenna Effect in VLSI
VLSI
Physical-Design
ASIC
Antenna-Effect
DRC
Jul 23, 2025
Aspect Ratio in VLSI Physical Design
VLSI
Physical-Design
ASIC
Aspect-Ratio
Floorplanning
Jul 23, 2025
Assertion Coverage
VLSI
Verification
ASIC
Assertion-Coverage
SVA
Jul 23, 2025
Assertions in VLSI
VLSI
Verification
ASIC
Assertions
SVA
Jul 23, 2025
Asynchronous FIFOs
VLSI
Digital-Design
ASIC
FIFO
CDC
Metastability
Jul 23, 2025
Asynchronous Reset in VLSI
VLSI
Reset
Digital-Design
Asynchronous
Jul 23, 2025
Built-In Self-Test (BIST)
VLSI
Testing
ASIC
DFT
BIST
Jul 23, 2025
Backend Interview Questions
VLSI
Interview-Questions
Physical-Design
STA
Power-Signoff
Signal-Integrity
Jul 23, 2025
Blocking vs Non-blocking Assignments
Verilog
SystemVerilog
HDL
Digital-Design
VLSI
Jul 23, 2025
Bottom-up Synthesis
VLSI
Synthesis
ASIC
Design-Flow
Jul 23, 2025
Bridging Faults
VLSI
Testing
ASIC
Fault-Models
Jul 23, 2025
Bring-Up in VLSI
VLSI
Post-Silicon-Validation
Chip-Design
Semiconductor
Jul 23, 2025
Buffer Insertion
VLSI
Physical-Design
ASIC
Timing-Closure
Signal-Integrity
Jul 23, 2025
Clock Domain Crossing (CDC)
VLSI
Digital-Design
ASIC
Clocking
Metastability
Jul 23, 2025
Common Power Format (CPF)
VLSI
Low-Power-Design
ASIC
Power-Management
CPF
UPF
Jul 23, 2025
Central Processing Unit (CPU)
VLSI
Architecture
SoC
Processor
Microarchitecture
Jul 23, 2025
Clock Tree Synthesis (CTS)
VLSI
Physical-Design
CTS
Clocking
ASIC
Jul 23, 2025
Cache Coherency
VLSI
Architecture
CPU
GPU
Cache
Memory-Hierarchy
Jul 23, 2025
Capacitance in VLSI
VLSI
Physical-Design
ASIC
Interconnect
Timing
Power
Signal-Integrity
Jul 23, 2025
Cell Sizing
VLSI
Physical-Design
ASIC
Optimization
PPA
Jul 23, 2025
Chip Specification
VLSI
ASIC-Design
Chip-Specification
Design-Flow
Jul 23, 2025
Clock Buffers and Inverters
VLSI
Digital-Design
ASIC
Clocking
CTS
Jul 23, 2025
Clock Frequency
VLSI
Clocking
Timing
ASIC
Chip-Specification
Jul 23, 2025
Clock Path ECO
VLSI
Physical-Design
ASIC
ECO
Timing-Closure
Clocking
Jul 23, 2025
Code Coverage
VLSI
Verification
ASIC
Coverage
RTL
Jul 23, 2025
Combinational Logic
Digital-Logic
VLSI
Electronics
Combinational-Circuits
Memoryless-Logic
Jul 23, 2025
Combinational Loops
Digital-Logic
VLSI
ASIC
Timing-Analysis
Design-Flow
Jul 23, 2025
Constrained Random Verification (CRV)
VLSI
Verification
ASIC
CRV
UVM
Coverage
Jul 23, 2025
Control Logic
VLSI
Digital-Design
ASIC
Microarchitecture
FSM
Jul 23, 2025
Conventional Clock Tree Synthesis (CTS)
VLSI
Physical-Design
ASIC
CTS
Clocking
Timing
Jul 23, 2025
Core Utilization in VLSI
VLSI
Physical-Design
Floorplanning
Area-Optimization
Jul 23, 2025
Cost Target
VLSI
ASIC-Design
Economics
Manufacturing
Jul 23, 2025
Crosstalk Delay
VLSI
Signal-Integrity
Timing-Analysis
ASIC
Crosstalk
Jul 23, 2025
Crosstalk in VLSI
VLSI
Signal-Integrity
Physical-Design
ASIC
Noise
Jul 23, 2025
check_timing Command in STA
VLSI
STA
Timing-Analysis
ASIC
SDC