Top-down Synthesis

Simple Explanation (Gist)

Top-down synthesis is a hierarchical design approach where the entire chip is first synthesized at a high level, and then individual blocks are broken down and synthesized in detail, ensuring that the overall design constraints are met from the beginning.

Detailed Breakdown

• Context: In complex ASIC designs, it’s often impractical to synthesize the entire chip as a single flat design due to computational complexity and memory requirements. Hierarchical Synthesis approaches, like top-down and bottom-up, are used to manage this complexity.

• Process: Top-down synthesis typically involves the following steps:

  1. Top-Level Synthesis: The entire design (including all its hierarchical blocks) is synthesized at a high level. This initial synthesis provides a global view of the design, allowing the synthesis tool to perform initial optimizations and generate a preliminary Gate-Level Netlist.
  2. Constraint Propagation/Budgeting: Based on the top-level synthesis results and overall chip constraints (from SDC), the timing, area, and power budgets are allocated and propagated down to the individual sub-blocks. This ensures that each block has specific targets it needs to meet to satisfy the top-level requirements.
  3. Block-Level Synthesis: Each sub-block is then synthesized independently using its allocated constraints. This allows for parallel development and optimization of individual blocks.
  4. Integration and Verification: The synthesized netlists of the individual blocks are then integrated back into the top-level design. Comprehensive verification (e.g., Static Timing Analysis, Formal Verification) is performed at the top level to ensure that the integrated design meets all global constraints.
  5. Iteration: If any block fails to meet its allocated budget or if top-level integration reveals new issues, the budgets might be re-allocated, or individual blocks might be re-synthesized.

• Advantages:

  • Early Global Optimization: Allows for global optimization and constraint management from the start, reducing the risk of late-stage timing or congestion issues.
  • Predictable Performance: By budgeting constraints early, it provides a more predictable path to meeting overall chip performance goals.
  • Better PPA (Performance, Power, Area): Can lead to better overall PPA compared to pure bottom-up approaches, as global interactions are considered.
  • Reduced Iterations: Aims to minimize iterations between different design stages by ensuring consistency from top to bottom.
  • Easier Debugging: Issues can often be traced back to specific blocks with violated budgets.

• Disadvantages:

  • Accurate Budgeting: Requires accurate budgeting of constraints to individual blocks, which can be challenging and might require some initial trial-and-error.
  • Over-constraining: Blocks might be over-constrained if budgets are too tight, leading to sub-optimal PPA for individual blocks.
  • Complexity: Managing the hierarchical flow and constraint propagation can be complex.

• When to Use: Top-down synthesis is generally preferred for large, complex, and performance-critical designs where early timing closure and predictable results are paramount.

• Tools: Modern synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus) support both top-down and bottom-up hierarchical synthesis flows.

Further Reading

• Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®
• VLSI Physical Design: From Graph Partitioning to Timing Closure