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Tag: ASIC
165 items with this tag.
Jul 24, 2025
Characterization
ASIC
Post-Silicon
Testing
Jul 24, 2025
Clock Gating
ASIC
Low-Power-Design
Clocking
Jul 24, 2025
Clock Mesh
ASIC
CTS
Clocking
Physical-Design
Jul 24, 2025
Clock Shielding
ASIC
CTS
Clocking
Signal-Integrity
Jul 24, 2025
DFM
ASIC
Manufacturing
Physical-Verification
Jul 24, 2025
DFT Power Signoff
ASIC
DFT
Power
Signoff
Jul 24, 2025
DFT Principles in VLSI
VLSI
DFT
Testability
ASIC
Verification
Jul 24, 2025
Design for Test (DFT)
VLSI
DFT
Testability
ASIC
Verification
Jul 24, 2025
Design Rule Check (DRC)
VLSI
Physical-Verification
DRC
Manufacturing
ASIC
Jul 24, 2025
DRV Fixing in VLSI
VLSI
Physical-Design
DRC
Timing-Closure
ASIC
Jul 24, 2025
Data Path Design
VLSI
Physical-Design
Datapath
ASIC
Jul 24, 2025
Data and clock Path
ASIC
STA
Timing
Jul 24, 2025
Debugging in VLSI
VLSI
Verification
Debug
ASIC
Post-Silicon
Jul 24, 2025
Decap Planning in VLSI
VLSI
Physical-Design
Power-Integrity
Decaps
ASIC
Jul 24, 2025
Decaps in VLSI
VLSI
Power-Integrity
Decoupling-Capacitors
ASIC
Noise
Jul 24, 2025
Delay Models in VLSI
VLSI
Timing-Analysis
Delay
ASIC
Jul 24, 2025
Delay in VLSI
VLSI
Timing
Performance
ASIC
Jul 24, 2025
Detailed Routing
ASIC
Physical-Design
Routing
Jul 24, 2025
Directed Testing
VLSI
Verification
Test
ASIC
Jul 24, 2025
Dynamic Power in VLSI
VLSI
Power-Consumption
Low-Power-Design
ASIC
Jul 24, 2025
Engineering Change Order (ECO) in VLSI
VLSI
ASIC
Design-Flow
Manufacturing
Bug-Fix
Jul 24, 2025
Electrical Rule Check (ERC)
VLSI
Physical-Verification
Electrical-Check
ASIC
Jul 24, 2025
ESD Checks in VLSI
VLSI
ESD
Reliability
Physical-Verification
ASIC
Jul 24, 2025
ESD Checks
ASIC
Physical-Verification
Reliability
Jul 24, 2025
Finite State Machines (FSM)
ASIC
RTL-Design
Digital-Circuits
Jul 24, 2025
Failure Analysis
ASIC
Post-Silicon
Reliability
Jul 24, 2025
Fall Time
ASIC
Timing
Signal-Integrity
Jul 24, 2025
False Paths in STA
VLSI
Timing-Analysis
STA
ASIC
Timing-Exceptions
Jul 24, 2025
Fault Models in VLSI
VLSI
Test
DFT
Verification
ASIC
Jul 24, 2025
Floorplanning and Power Planning in VLSI
VLSI
Physical-Design
Floorplanning
Power-Planning
ASIC
Jul 24, 2025
Frontend Interview Questions
ASIC
Interview
Frontend
RTL
Verification
Synthesis
Jul 24, 2025
Functional Coverage
ASIC
Verification
UVM
Jul 24, 2025
Halo (Keep Out Margins)
ASIC
Physical-Design
Placement
Jul 24, 2025
Handshake Protocol
ASIC
RTL-Design
CDC
Jul 24, 2025
Hard Blockage
ASIC
Physical-Design
Placement
Jul 24, 2025
Hold Time
ASIC
STA
Timing
Jul 24, 2025
Logic Built-In Self-Test (LBIST)
ASIC
DFT
Test
Jul 24, 2025
Logical Equivalence Checking (LEC)
ASIC
Verification
Formal-Verification
Jul 24, 2025
LEF (Library Exchange Format)
ASIC
Physical-Design
File-Formats
Jul 24, 2025
LVS (Layout Versus Schematic)
ASIC
Physical-Verification
Jul 24, 2025
Launch and Capture Path
ASIC
STA
Timing
Jul 24, 2025
Level Shifters
ASIC
Low-Power
Synthesis
Jul 24, 2025
Library Consistency
ASIC
Physical-Design
Sanity-Checks
Jul 24, 2025
Linking Checks
ASIC
STA
Timing
Jul 24, 2025
Linting
ASIC
RTL-Design
Verification
Jul 24, 2025
Logic Optimization
ASIC
Synthesis
Optimization
Jul 24, 2025
Low Power Design
ASIC
Low-Power
Design
Jul 24, 2025
Low Power Synthesis
ASIC
Synthesis
Low-Power
Jul 24, 2025
Low Power Verification
ASIC
Verification
Low-Power
Jul 24, 2025
Memory Built-In Self-Test (MBIST)
ASIC
DFT
Test
Jul 24, 2025
Macro Placement
ASIC
Physical-Design
Placement
Jul 24, 2025
Mask Generation
ASIC
Manufacturing
Tape-Out
Jul 24, 2025
Max Fanout
ASIC
STA
Design-Rules
Jul 24, 2025
Metal-Only ECO
ASIC
ECO
Physical-Design
Jul 24, 2025
Metal Fill Verification
ASIC
Physical-Verification
Manufacturing
Jul 24, 2025
Metastability
ASIC
RTL-Design
CDC
Jul 24, 2025
OVM (Open Verification Methodology)
ASIC
Verification
Methodology
Jul 24, 2025
Power-Aware Formal Verification (PAFV)
ASIC
Verification
Low-Power
Formal-Verification
Jul 24, 2025
Partial Blockage
ASIC
Physical-Design
Placement
Jul 24, 2025
Partitioning
ASIC
Physical-Design
Floorplanning
Jul 24, 2025
Physical Design (Backend)
ASIC
Physical-Design
Backend
Jul 24, 2025
Placement Blockages
ASIC
Physical-Design
Placement
Jul 24, 2025
Post-Silicon Validation
ASIC
Post-Silicon
Verification
Jul 24, 2025
Power Domains
ASIC
Low-Power
UPF
Jul 24, 2025
Power Supply Noise
ASIC
Power-Integrity
Noise
Jul 24, 2025
Process Variation
ASIC
Manufacturing
Reliability
Jul 24, 2025
Propagation Delay
ASIC
Timing
Delay
Jul 24, 2025
RTL Design
ASIC
Frontend
RTL
Jul 24, 2025
Race Conditions
ASIC
Digital-Circuits
Timing
Jul 24, 2025
Register File
ASIC
Architecture
Memory
Jul 24, 2025
Retention Cells
ASIC
Physical-Design
Low-Power
Jul 24, 2025
Retention Registers
ASIC
Low-Power-Design
Power-Management
Jul 24, 2025
Rise Time
ASIC
Timing
Signal-Integrity
Jul 24, 2025
Routing Layers
ASIC
Physical-Design
Routing
Jul 24, 2025
Routing Optimizations
ASIC
Physical-Design
Routing
Jul 24, 2025
Routing
ASIC
Physical-Design
Routing
Jul 24, 2025
SDC Checks
ASIC
Physical-Design
SDC
Verification
Jul 24, 2025
SDC
ASIC
STA
Constraints
Jul 24, 2025
SI Double Switching
ASIC
STA
Signal-Integrity
Jul 24, 2025
SPEF
ASIC
STA
Physical-Design
File-Format
Jul 24, 2025
STA
ASIC
STA
Timing
Jul 24, 2025
SVA
ASIC
Functional-Verification
SystemVerilog
Jul 24, 2025
Samsung
ASIC
Foundry
Semiconductor
Jul 24, 2025
Sanity Checks
ASIC
Physical-Design
Verification
Jul 24, 2025
Scan Chains
ASIC
DFT
Testing
Jul 24, 2025
Scan Compression
ASIC
DFT
Testing
Jul 24, 2025
Scan Insertion
ASIC
DFT
Testing
Jul 24, 2025
Sequential Logic
ASIC
Digital-Circuits
Logic
Jul 24, 2025
Setup Time
ASIC
STA
Timing
Jul 24, 2025
Shmoo Plots
ASIC
Post-Silicon
Validation
Testing
Jul 24, 2025
Sign Off
ASIC
Signoff
Verification
Jul 24, 2025
Signal Integrity
ASIC
Physical-Design
STA
Jul 24, 2025
Simulation
ASIC
Functional-Verification
Simulation
Jul 24, 2025
Soft Blockage
ASIC
Physical-Design
Floorplanning
Jul 24, 2025
Spare Cells
ASIC
Physical-Design
ECO
Jul 24, 2025
Standard Cell Library
ASIC
Synthesis
Physical-Design
Jul 24, 2025
Stuck-at Faults
ASIC
DFT
Fault-Models
Jul 24, 2025
Synchronizers
ASIC
CDC
Verification
Jul 24, 2025
Synchronous Reset
ASIC
RTL-Design
Reset
Jul 24, 2025
Synthesis
ASIC
Frontend
Synthesis
Jul 24, 2025
Synthesizable vs Non-synthesizable constructs
ASIC
RTL-Design
Synthesis
Jul 24, 2025
SystemVerilog
ASIC
HDL
Verification
Jul 24, 2025
TSMC
ASIC
Foundry
Semiconductor
Jul 24, 2025
Tape Out & Manufacturing
ASIC
Manufacturing
Tape-Out
Jul 24, 2025
Technology File
ASIC
Foundry
Physical-Design
Jul 24, 2025
Technology Mapping
ASIC
Synthesis
Optimization
Jul 24, 2025
Tempus
ASIC
STA
EDA-Tool
Jul 24, 2025
Test Coverage
ASIC
Functional-Verification
DFT
Jul 24, 2025
Test Techniques
ASIC
Functional-Verification
Testing
Jul 24, 2025
Timing ECO
ASIC
ECO
STA
Jul 24, 2025
Timing Library
ASIC
STA
File-Format
Jul 24, 2025
Timing Paths
ASIC
STA
Timing
Jul 24, 2025
Timing Window File
ASIC
STA
File-Format
Jul 24, 2025
Timing-Driven Routing
ASIC
Physical-Design
Routing
Timing
Jul 24, 2025
Top-down Synthesis
ASIC
Synthesis
Hierarchical
Jul 24, 2025
Total Power
ASIC
Power
Low-Power
Jul 24, 2025
Transition Faults
ASIC
DFT
Fault-Models
Jul 24, 2025
Transition
ASIC
STA
Timing
Jul 24, 2025
Tweaker
ASIC
STA
ECO
EDA-Tool
Jul 24, 2025
UPF
ASIC
Low-Power
File-Format
Jul 24, 2025
UVM Agent
ASIC
Functional-Verification
UVM
Jul 24, 2025
UVM Components
ASIC
Functional-Verification
UVM
Jul 24, 2025
UVM Driver
ASIC
Functional-Verification
UVM
Jul 24, 2025
UVM Monitor
ASIC
Functional-Verification
UVM
Jul 24, 2025
UVM Scoreboard
ASIC
Functional-Verification
UVM
Jul 24, 2025
UVM Sequencer
ASIC
Functional-Verification
UVM
Jul 24, 2025
UVM
ASIC
Functional-Verification
Methodology
Jul 24, 2025
Unclocked Flops
ASIC
STA
Timing
Jul 24, 2025
Unconstrained Endpoints
ASIC
STA
Timing
Jul 24, 2025
Useful Skew
ASIC
CTS
STA
Timing
Jul 24, 2025
VHDL
ASIC
HDL
RTL
Jul 24, 2025
Verilog
ASIC
HDL
RTL
Jul 24, 2025
WLM
ASIC
Synthesis
Timing
Jul 24, 2025
Wafer Sort
ASIC
Manufacturing
Testing
Jul 24, 2025
Yield Analysis
ASIC
Manufacturing
Post-Silicon
Jul 24, 2025
Chip
ASIC
VLSI
Integrated-Circuit
Jul 23, 2025
Automatic Test Equipment (ATE)
VLSI
Testing
ASIC
ATE
Post-Silicon-Validation
Jul 23, 2025
Automatic Test Pattern Generation (ATPG)
VLSI
Testing
ASIC
DFT
ATPG
Jul 23, 2025
Activity Vectors
VLSI
Power-Analysis
ASIC
SAIF
VCD
Jul 23, 2025
Advanced Verification in VLSI
VLSI
Verification
ASIC
UVM
Formal
PSS
AI
Jul 23, 2025
Antenna Effect in VLSI
VLSI
Physical-Design
ASIC
Antenna-Effect
DRC
Jul 23, 2025
Aspect Ratio in VLSI Physical Design
VLSI
Physical-Design
ASIC
Aspect-Ratio
Floorplanning
Jul 23, 2025
Assertion Coverage
VLSI
Verification
ASIC
Assertion-Coverage
SVA
Jul 23, 2025
Assertions in VLSI
VLSI
Verification
ASIC
Assertions
SVA
Jul 23, 2025
Asynchronous FIFOs
VLSI
Digital-Design
ASIC
FIFO
CDC
Metastability
Jul 23, 2025
Built-In Self-Test (BIST)
VLSI
Testing
ASIC
DFT
BIST
Jul 23, 2025
Bottom-up Synthesis
VLSI
Synthesis
ASIC
Design-Flow
Jul 23, 2025
Bridging Faults
VLSI
Testing
ASIC
Fault-Models
Jul 23, 2025
Buffer Insertion
VLSI
Physical-Design
ASIC
Timing-Closure
Signal-Integrity
Jul 23, 2025
Clock Domain Crossing (CDC)
VLSI
Digital-Design
ASIC
Clocking
Metastability
Jul 23, 2025
Common Power Format (CPF)
VLSI
Low-Power-Design
ASIC
Power-Management
CPF
UPF
Jul 23, 2025
Clock Tree Synthesis (CTS)
VLSI
Physical-Design
CTS
Clocking
ASIC
Jul 23, 2025
Capacitance in VLSI
VLSI
Physical-Design
ASIC
Interconnect
Timing
Power
Signal-Integrity
Jul 23, 2025
Cell Sizing
VLSI
Physical-Design
ASIC
Optimization
PPA
Jul 23, 2025
Clock Buffers and Inverters
VLSI
Digital-Design
ASIC
Clocking
CTS
Jul 23, 2025
Clock Frequency
VLSI
Clocking
Timing
ASIC
Chip-Specification
Jul 23, 2025
Clock Path ECO
VLSI
Physical-Design
ASIC
ECO
Timing-Closure
Clocking
Jul 23, 2025
Code Coverage
VLSI
Verification
ASIC
Coverage
RTL
Jul 23, 2025
Combinational Loops
Digital-Logic
VLSI
ASIC
Timing-Analysis
Design-Flow
Jul 23, 2025
Constrained Random Verification (CRV)
VLSI
Verification
ASIC
CRV
UVM
Coverage
Jul 23, 2025
Control Logic
VLSI
Digital-Design
ASIC
Microarchitecture
FSM
Jul 23, 2025
Conventional Clock Tree Synthesis (CTS)
VLSI
Physical-Design
ASIC
CTS
Clocking
Timing
Jul 23, 2025
Crosstalk Delay
VLSI
Signal-Integrity
Timing-Analysis
ASIC
Crosstalk
Jul 23, 2025
Crosstalk in VLSI
VLSI
Signal-Integrity
Physical-Design
ASIC
Noise
Jul 23, 2025
check_timing Command in STA
VLSI
STA
Timing-Analysis
ASIC
SDC