VHDL

Simple Explanation (Gist)

VHDL (VHSIC Hardware Description Language) is a powerful Hardware Description Language used to describe the behavior and structure of digital electronic systems, enabling designers to model circuits for Simulation and Synthesis.

Detailed Breakdown

• What is VHDL?: VHDL (IEEE 1076) is a textual language used for describing digital electronic circuits and systems. It is one of the two dominant HDLs (the other being Verilog) used in the design and verification of ASICs and FPGAs. VHDL was initially developed by the U.S. Department of Defense for documenting hardware designs and later became a standard for design and simulation.

• Levels of Abstraction:

  1. Behavioral Level: Describes the circuit’s behavior using sequential statements (e.g., process statements, if-then-else, case statements). This is the highest level of abstraction.
  2. Register Transfer Level (RTL): Describes the flow of data between registers and the combinational logic that processes this data. This is the most common level for synthesizable designs.
  3. Dataflow Level: Describes the flow of data using concurrent signal assignments.
  4. Structural Level: Describes the circuit as an interconnection of components (e.g., gates, flip-flops, or other modules).

• Key Constructs and Concepts:

  • Entity and Architecture: A VHDL design unit consists of an entity (defining the interface of the hardware block) and one or more architectures (describing its behavior or structure).
  • Ports: Define the interface of an entity (input, output, inout).
  • Data Types: Strong typing is a key feature of VHDL, with various predefined types (e.g., BIT, STD_LOGIC, INTEGER, BOOLEAN) and user-defined types.
  • Processes: Sequential blocks of code that execute concurrently. They are sensitive to changes in signals listed in their sensitivity list.
  • Concurrent Statements: Statements that execute in parallel, typically used for dataflow descriptions.
  • Packages: Used to group common declarations (e.g., data types, functions, components) for reuse.
  • Generics: For creating configurable and reusable modules.

• Usage in ASIC Design Flow:

  • RTL Design: VHDL is widely used to write the RTL code for the design under test.
  • Functional Verification: Used to create testbenches for simulating the RTL and gate-level netlists.
  • Synthesis: Synthesizable VHDL code is translated into a Gate-Level Netlist by synthesis tools.
  • Gate-Level Netlist Representation: The output of synthesis can be a VHDL netlist.

• Comparison with Verilog: While both are HDLs, VHDL is often considered more verbose and strongly typed than Verilog. VHDL has better support for large-scale system modeling and formal verification, while Verilog is often preferred for its C-like syntax and ease of use for gate-level descriptions.

Further Reading

• The Designer’s Guide to VHDL
• Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog