Stuck-at Faults
Simple Explanation (Gist)
Stuck-at faults are a fundamental fault model used in digital circuit testing where a signal line or a gate input/output is permanently fixed at a logic 0 (stuck-at-0) or a logic 1 (stuck-at-1), regardless of the actual circuit behavior.
Detailed Breakdown
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Purpose: The stuck-at fault model is widely used in Design for Test because it is simple, effective, and covers a significant percentage of physical defects that can occur during semiconductor manufacturing. It simplifies the process of ATPG and Test Coverage calculation.
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Types of Stuck-at Faults:
- Stuck-at-0 (SA0): The signal line or node is permanently fixed at a logic low (0) value.
- Stuck-at-1 (SA1): The signal line or node is permanently fixed at a logic high (1) value.
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Location of Faults: Stuck-at faults can occur at various points in a digital circuit:
- Gate Inputs: An input pin of a logic gate is stuck at 0 or 1.
- Gate Outputs: The output pin of a logic gate is stuck at 0 or 1.
- Net Segments: Any segment of a wire (net) connecting two or more components is stuck at 0 or 1.
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How Stuck-at Faults Occur (Physical Defects):
- Shorts: A short circuit to ground (VSS) can cause a stuck-at-0. A short to power (VDD) can cause a stuck-at-1.
- Opens: An open circuit can cause a floating node, which might behave as a stuck-at-0 or stuck-at-1 depending on the technology and surrounding circuitry.
- Transistor Failures: A transistor permanently stuck ON or OFF can manifest as a stuck-at fault.
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Testing for Stuck-at Faults:
- Activation: A test pattern (input vector) is applied to the circuit to create a logic value at the fault site that is opposite to the stuck-at value. For example, to test for a stuck-at-0 fault, a logic 1 must be driven to the fault site.
- Propagation: The effect of the fault (the incorrect logic value at the fault site) must then be propagated through the combinational logic to an observable output pin (or a scan chain flip-flop) where it can be detected by the Automatic Test Equipment.
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Fault Coverage: The percentage of detectable stuck-at faults in a design is a key metric for test quality. Scan Chains are widely used to improve the controllability and observability of internal nodes, thereby increasing stuck-at fault coverage.
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Limitations: While widely used, the stuck-at fault model does not cover all possible physical defects. Other fault models, such as Transition Faults (for delay defects) and Bridging Faults (for shorts between two signal lines), are used to complement stuck-at testing.