ASIC

Tag: Timing-Analysis

6 items with this tag.

  • Jul 24, 2025

    Delay Models in VLSI

    • VLSI
    • Timing-Analysis
    • Delay
    • ASIC
  • Jul 24, 2025

    False Paths in STA

    • VLSI
    • Timing-Analysis
    • STA
    • ASIC
    • Timing-Exceptions
  • Jul 24, 2025

    Hold Time

    • VLSI
    • STA
    • Timing-Analysis
  • Jul 23, 2025

    Combinational Loops

    • Digital-Logic
    • VLSI
    • ASIC
    • Timing-Analysis
    • Design-Flow
  • Jul 23, 2025

    Crosstalk Delay

    • VLSI
    • Signal-Integrity
    • Timing-Analysis
    • ASIC
    • Crosstalk
  • Jul 23, 2025

    check_timing Command in STA

    • VLSI
    • STA
    • Timing-Analysis
    • ASIC
    • SDC

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