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Engineering Change Order (ECO) in VLSI

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Engineering Change Order (ECO) in VLSI

1. Simple Explanation (Gist)

An Engineering Change Order (ECO) in VLSI (Very Large Scale Integration) is a critical process used to implement last-minute design modifications or bug fixes on a semiconductor chip with minimal disruption to the existing design and manufacturing flow, saving significant time and cost compared to a full redesign.

2. Detailed Breakdown

Purpose of ECOs

ECOs are necessary to address issues discovered late in the design cycle, such as functional errors, timing violations, power consumption problems, or to incorporate minor specification changes or new customer requirements.

Why ECOs are Preferred

Instead of re-invoking the entire VLSI design flow (which can take months and be very costly), ECOs allow for targeted changes, preserving previously optimized efforts and accelerating time-to-market.

Types of ECOs

  • All-Layer ECO (Unconstrained ECO): This type of ECO involves changes across all layers of the chip design and is typically done before mask generation. There are no restrictions on the changes permitted in the Layout.
  • Metal-Only ECO (Freeze Silicon ECO/Metal Mask ECO): This is a more cost-effective and time-saving approach, implemented after tape-out (when the design is sent for fabrication). It involves changes only to the metal layers, leaving the base layers untouched. This often utilizes pre-placed “spare cells” in the design.

ECO Process Flow (General Steps)

  1. Identify Change: A design bug is found, or a specification change is required.
  2. RTL and Netlist Modification: The Register Transfer Level (RTL) code is updated, and the gate-level netlist is modified accordingly.
  3. Verification: The modified netlist undergoes formal and functional verification to ensure correctness.
  4. Delta Implementation: The differences (delta) between the original and modified netlists are identified.
  5. Incremental Placement and Routing: The logic causing the difference is incrementally placed, and connections are modified, often focusing on metal layers. This may involve using spare cells.
  6. Signoff Closure: ECOs are crucial in the final signoff phase to close any remaining timing, DRC (Design Rule Check), and IR (IR drop) violations.

Benefits of ECOs

  • Efficiency: Minimal rework is required.
  • Time-to-Market: Significantly reduces the design cycle time.
  • Cost Savings: Avoids the high cost of a full chip respin.

Challenges

Despite their benefits, ECOs can be computationally complex and have stringent physical restrictions, making automation and robust tools essential.

3. Conclusion

Engineering Change Orders are an indispensable part of the VLSI design process, enabling designers to efficiently and cost-effectively incorporate late-stage modifications or fixes to integrated circuits. By strategically applying changes, often leveraging metal-only modifications and spare cells, ECOs help maintain aggressive product development schedules and reduce manufacturing costs, ultimately ensuring the timely delivery of functional and optimized chips.

Further Reading

  • VLSI Physical Design: From Graph Partitioning to Timing Closure by Andrew B. Kahng, Jens Lienig, Igor L. Markov, and Jin Hu
  • CMOS VLSI Design: A Circuits and Systems Perspective by Neil Weste & David Harris
  • VLSI Pro - ECO
  • ChipEdge - What is ECO?
  • Synopsys - ECO

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