ASIC

Tag: Low-Power-Design

11 items with this tag.

  • Jul 24, 2025

    Conformal Low Power (CLP) Checks

    • VLSI
    • Low-Power-Design
    • Power-Management
    • Verification
    • EDA
  • Jul 24, 2025

    Clock Gating

    • ASIC
    • Low-Power-Design
    • Clocking
  • Jul 24, 2025

    Dynamic Power in VLSI

    • VLSI
    • Power-Consumption
    • Low-Power-Design
    • ASIC
  • Jul 24, 2025

    Isolation Cells

    • VLSI
    • Low-Power-Design
    • Synthesis
  • Jul 24, 2025

    Multi-Vt Cells

    • VLSI
    • Low-Power-Design
    • Standard-Cells
  • Jul 24, 2025

    Multi-voltage Design

    • VLSI
    • Low-Power-Design
    • Power-Management
  • Jul 24, 2025

    Operand Isolation

    • VLSI
    • Low-Power-Design
    • Power-Management
  • Jul 24, 2025

    Power Gating

    • VLSI
    • Low-Power-Design
    • Power-Management
  • Jul 24, 2025

    Power Types

    • VLSI
    • Power-Consumption
    • Low-Power-Design
  • Jul 24, 2025

    Retention Registers

    • ASIC
    • Low-Power-Design
    • Power-Management
  • Jul 23, 2025

    Common Power Format (CPF)

    • VLSI
    • Low-Power-Design
    • ASIC
    • Power-Management
    • CPF
    • UPF

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