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Tag: Physical-Design
59 items with this tag.
Jul 24, 2025
CTS Tools
VLSI
Physical-Design
CTS
EDA-Tools
Clocking
Jul 24, 2025
Clock Mesh
ASIC
CTS
Clocking
Physical-Design
Jul 24, 2025
DDR (Double Data Rate) SDRAM
VLSI
Memory
Interface
Physical-Design
SoC
Jul 24, 2025
Design Exchange Format (DEF)
VLSI
Physical-Design
File-Format
EDA
Jul 24, 2025
DRV Fixing in VLSI
VLSI
Physical-Design
DRC
Timing-Closure
ASIC
Jul 24, 2025
Data Path Design
VLSI
Physical-Design
Datapath
ASIC
Jul 24, 2025
Decap Planning in VLSI
VLSI
Physical-Design
Power-Integrity
Decaps
ASIC
Jul 24, 2025
Detailed Routing
ASIC
Physical-Design
Routing
Jul 24, 2025
Die Size Estimation in VLSI
VLSI
Physical-Design
Semiconductor-Manufacturing
Die-Size
Estimation
Jul 24, 2025
Electromigration in VLSI
VLSI
Reliability
Interconnect
Physical-Design
Power-Integrity
Jul 24, 2025
Floorplanning and Power Planning in VLSI
VLSI
Physical-Design
Floorplanning
Power-Planning
ASIC
Jul 24, 2025
Flylines
VLSI
Physical-Design
Floorplanning
Jul 24, 2025
Global Routing
VLSI
Physical-Design
Routing
Jul 24, 2025
H-Tree
VLSI
Clock-Tree-Synthesis
Physical-Design
Jul 24, 2025
Halo (Keep Out Margins)
ASIC
Physical-Design
Placement
Jul 24, 2025
Hard Blockage
ASIC
Physical-Design
Placement
Jul 24, 2025
High-Fanout Net Synthesis (HFNS)
VLSI
Physical-Design
Placement
Jul 24, 2025
LEF (Library Exchange Format)
ASIC
Physical-Design
File-Formats
Jul 24, 2025
Library Consistency
ASIC
Physical-Design
Sanity-Checks
Jul 24, 2025
MSCTS
VLSI
Clock-Tree-Synthesis
Physical-Design
Jul 24, 2025
Macro Placement
ASIC
Physical-Design
Placement
Jul 24, 2025
Metal Fill
VLSI
Physical-Design
Manufacturing
Jul 24, 2025
Metal-Only ECO
ASIC
ECO
Physical-Design
Jul 24, 2025
NDR
VLSI
Physical-Design
Routing
Jul 24, 2025
Netlist Input
VLSI
Physical-Design
Design-Flow
Jul 24, 2025
Noise
VLSI
Signal-Integrity
Physical-Design
Jul 24, 2025
Partial Blockage
ASIC
Physical-Design
Placement
Jul 24, 2025
Partitioning
ASIC
Physical-Design
Floorplanning
Jul 24, 2025
Physical Design (Backend)
ASIC
Physical-Design
Backend
Jul 24, 2025
Physical Synthesis
VLSI
Synthesis
Physical-Design
Jul 24, 2025
Physical Verification
VLSI
Physical-Design
Verification
Jul 24, 2025
Pin Assignment
VLSI
Physical-Design
Floorplanning
Jul 24, 2025
Placement Blockages
ASIC
Physical-Design
Placement
Jul 24, 2025
Placement
VLSI
Physical-Design
P-and-R
Jul 24, 2025
Pre-Placement & Sanity Checks
VLSI
Physical-Design
Verification
Jul 24, 2025
Retention Cells
ASIC
Physical-Design
Low-Power
Jul 24, 2025
Routing Layers
ASIC
Physical-Design
Routing
Jul 24, 2025
Routing Optimizations
ASIC
Physical-Design
Routing
Jul 24, 2025
Routing
ASIC
Physical-Design
Routing
Jul 24, 2025
SDC Checks
ASIC
Physical-Design
SDC
Verification
Jul 24, 2025
SPEF
ASIC
STA
Physical-Design
File-Format
Jul 24, 2025
Sanity Checks
ASIC
Physical-Design
Verification
Jul 24, 2025
Signal Integrity
ASIC
Physical-Design
STA
Jul 24, 2025
Soft Blockage
ASIC
Physical-Design
Floorplanning
Jul 24, 2025
Spare Cells
ASIC
Physical-Design
ECO
Jul 24, 2025
Standard Cell Library
ASIC
Synthesis
Physical-Design
Jul 24, 2025
Technology File
ASIC
Foundry
Physical-Design
Jul 24, 2025
Timing-Driven Routing
ASIC
Physical-Design
Routing
Timing
Jul 23, 2025
Antenna Effect in VLSI
VLSI
Physical-Design
ASIC
Antenna-Effect
DRC
Jul 23, 2025
Aspect Ratio in VLSI Physical Design
VLSI
Physical-Design
ASIC
Aspect-Ratio
Floorplanning
Jul 23, 2025
Backend Interview Questions
VLSI
Interview-Questions
Physical-Design
STA
Power-Signoff
Signal-Integrity
Jul 23, 2025
Buffer Insertion
VLSI
Physical-Design
ASIC
Timing-Closure
Signal-Integrity
Jul 23, 2025
Clock Tree Synthesis (CTS)
VLSI
Physical-Design
CTS
Clocking
ASIC
Jul 23, 2025
Capacitance in VLSI
VLSI
Physical-Design
ASIC
Interconnect
Timing
Power
Signal-Integrity
Jul 23, 2025
Cell Sizing
VLSI
Physical-Design
ASIC
Optimization
PPA
Jul 23, 2025
Clock Path ECO
VLSI
Physical-Design
ASIC
ECO
Timing-Closure
Clocking
Jul 23, 2025
Conventional Clock Tree Synthesis (CTS)
VLSI
Physical-Design
ASIC
CTS
Clocking
Timing
Jul 23, 2025
Core Utilization in VLSI
VLSI
Physical-Design
Floorplanning
Area-Optimization
Jul 23, 2025
Crosstalk in VLSI
VLSI
Signal-Integrity
Physical-Design
ASIC
Noise